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5,028 Views 3 Replies Last post: Feb 20, 2012 7:40 PM by yubaobaobao627 RSS
stefano.stanzione Contributor 5 posts since
Sep 21, 2010
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Sep 21, 2010 1:50 AM

Parasitic EXtraction of a layout without schemtic source

Hi all,

I am trying to create an interconnect capacitance in my circuit.
So I created a schematic view with only the PINs (PLUS and MINUS) and I created the layout of the cell.
My aim is to extract the parasitics for having a schematic to use in simulations.
The problem is that, when I try to run the Calibre PEX (as for the LVS), I get:
"ERROR: Nothing in source.
ERROR: Nothing in layout. "
How can I solve the problem of extracting the parasitics from my cell?

Thanks,
Stefano

chris_balcom jedi 424 posts since
Apr 3, 2008
Currently Being Moderated
Sep 28, 2010 3:19 PM in response to: stefano.stanzione
Re: Parasitic EXtraction of a layout without schemtic source

Hi Stefano,

 

I don't have xRC experience but it sounded like "black box" extraction. when I searched for that on Supportnet I found a TechNote that referred to the xRC User Manual section called "Running Gate-Level Extraction".

 

Do you think that might apply?

yubaobaobao627 Lurker 1 posts since
Feb 20, 2012
Currently Being Moderated
Feb 20, 2012 7:40 PM in response to: stefano.stanzione
Re: Parasitic EXtraction of a layout without schemtic source

Hi, Stefano,

     I am a student from Tsinghua university,this days i was facing the same problem with you. I found that the calibre pex always reported the error:noting in source,then I checked the calibre input files,and changed it with the .sp file created from the lvs. Finally,it worked. So I guess your problem may be the same. Good luck!

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