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3,826 Views 2 Replies Last post: Feb 2, 2011 5:34 AM by yashoda.narvankar RSS
yashoda.narvankar Contributor 9 posts since
Dec 22, 2010
Currently Being Moderated

Jan 31, 2011 3:28 AM

DDR3 Differential clock fails for initial clock cycles...

Hi,

 

I am performing SI for Differential clock for DDR3 signal. The topology is daisy chain, with the processor connected to 5 DDR3 chips and a termination is kept at the end.

 

On simuating, the differential signal crosses threshold (+/-200mV) for the initial 3-4 cycles, after which the clock signal passes for all the next cycles.

 

So, the question is that, is it alright if we ignore these initial cycles wherein the signal fails?

 

Thanks.

weston_beal Aficionado 165 posts since
Sep 4, 2008
Currently Being Moderated
Jan 31, 2011 2:06 PM in response to: yashoda.narvankar
Re: DDR3 Differential clock fails for initial clock cycles...

Think about how the simulation relates to your real system. In the real system, do you care about the first few bits when it starts up, or do you care about how the system performs after 1 microsecond?

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