Hi,

I am performing SI for Differential clock for DDR3 signal. The topology is daisy chain, with the processor connected to 5 DDR3 chips and a termination is kept at the end.

On simuating, the differential signal crosses threshold (+/-200mV) for the initial 3-4 cycles, after which the clock signal passes for all the next cycles.

So, the question is that, is it alright if we ignore these initial cycles wherein the signal fails?

Thanks.