"noxref" nets in Calibre xRC netlists cause back-annotation in PrimeTime to fail

Version 2

    Regarding items that may appear in the Calibre xRC parasitic netlist containing “noxref” in their name:

    If you are attempting back-annotation of your layout parasitics to a schematic (SOURCE) database within a tool such as PrimeTime, for example, you can sometimes experience "noxref" named items in the parasitic netlist from Calibre xRC limiting your attempts to perform back-annotation successfully.

    There can be cases in which the layout circuitry does not map exactly to the schematic node for node, but even so is equivalent and passes LVS.  Usually SVRF statements such as LVS REDUCE PARALLEL/SERIAL or LVS REDUCE SPLIT GATES can cause reduction of the layout dataset to match the source allowing LVS to pass.   The task of parasitic extraction is to produce a netlist that exactly matches the layout with parasitics added.  In cases where reduction of the layout dataset is happening for LVS to pass, the parasitic netlist produced by Calibre xRC will contain layout circuit nodes that do not have a cross-reference in the source data.  Calibre xRC will identify these items with "noxref" in their names within the output parasitic netlist.

    In such cases back-annotation to a schematic dataset using the normal layout based parasitic extraction netlist will produce errors regarding the "noxref" items.

    However, you can still successfully back-annotate your schematic database with your layout parasitics by requesting a parasitic netlist from Calibre xRC that exactly matches the schematic (SOURCE) network.

    This can be done as follows:

    In the v2008.4 release and following
        use the PEX NETLIST statement keyword SOURCEBASED
        to enable the SOURCEBASED flow
    or instead
        use the PEX NETLIST statement keyword SCHEMATICONLY
        to enable the SCHEMATICONLY flow.

    SOURCEBASED
    specifies a parasitic netlist based on the LVS source hierarchy, with intentional device parameters extracted and back-annotated from the SOURCE.


    SCHEMATICONLY
    specifies a parasitic netlist based on the LVS source hierarchy, with intentional device parameters extracted and back-annotated from

    the LAYOUT.

    In Calibre Interactive – PEX, these choices appear  under:

           Outputs  >  Netlist  >  Use Names From:  

    For more detail on these choices please review TechNote MG543224
    Eliminating noxref items from Calibre xRC netlists for backannotation flows


    In releases prior to v2008.4 the source based flow can be specified using:

       setenv PEX_FMT_SOURCE_BASED_FLOW ON


    This is an environment setting to be made before running parasitic extraction with Calibre xRC.


    The possible risk in running a flow that is based on the network in the schematics is that layout nodes which are not represented in the SOURCE will not be represented in the parasitic results, and will affect accuracy accordingly.


    The benefit in running a flow that is based on the network in the schematics is that you get to back-annotate your schematic database with parasitics and perform static timing analysis in tool designed for that purpose.


    Please note that the above environment variable has been deprecated with the v2008.4 release.