It's so easy to assembly the channel for IBIS-AMI analysis in HL 8.1 GHz. an excellent feature to make every hardware engineer can use it without traning !
S parameters have passed passivity and casuality checks, only there is small reciprocity fbetween 6G-10G. For 3.25 Gps, I got the clear eye where you can see 2 crossovers. After increasing bit rate, only one crossover. I don't really know why
The eye diagram that you see is shifted as a result of the clock times produced by the AMI model. This relates to the CDR behavior within the receiver and we are only displaying what the AMI model is telling us to display. This is not a limitation of our tool because we are implementing what the AMI specification defines (input data signal is sampled at exactly one half clock period after a clock time) , rather this model isn't behaving appropriately relative to the AMI specification.
Much thanks for detailed explanation. I got understand why the crossover not visible. I also run Xilinx V6 GTP IBIS-AMI model on HL 8.1. It can display 2 crossovers what ever decreasing bit rate or increasing bit rate and correlate with measured eyes, it's very match! now our engineer love to use HL8.1 it in thier daily works.
What did you do to fix this?
I am having the same issue modeling Altera GT part at 11.3Gbps. Looking through the IBIS AMI model spec it looks like the sample interval and bit_time are passed from the EDA platform (Hyperlynx) to the shared library (AMI algorithm), not the other way around.
I guess the IBIS-AMI kit was created by Sisoft. I really don't how to do.
The “clock_times” can be produced by the AMI DLL. This is the vector that is used to sample the output waveform data. The details relating to clock times can be found within BIRD112 http://eda.org/pub/ibis/birds/bird112.txt
As to your specific issue with this Altera IBIS AMI model Mentor Customer support may be able to help you.
I get the IBIS-AMI kit 0.6 from Altera. The 0.6 version now centers the eye diagram. I have verified it on Hyperlynx 8.1.1
Altera Release History see below:
Modified CDR Settings
- Removed internal CDR settings
- Included PLL Bandwidth mode selection
Print warning, error and AMI parameters to log file.
Center eye diagram
Included windows 64bit executable
can anyboby on this discussion tell me what are the requirements for performing IBIS-AMI channel analysis. I want to simulate LVDS signals transmitted from Virtex 5 GTP transceiver to a V5 GTP receiver connected on a backplane through PCI-e. I have IBIS-AMI models for V5 GTP transceiver provided by xilinx but I dont have the s- parameter package models for driver and receiver and also I dont have the model for PCI-e connector. from where can I get my required models? and what model should I use for the channel?
Are you sure your V5 GTP interface is not CML?
The Xilinx Signal Integrity Simulation Kit includes package parasitic file in Touchstone format (.s4p).
You get s-parameter data from the connector vendor, they probably have it if it is intended for GHz rate signals. They are often not posted on www, you may have to work with a sales rep to get the data.
Hyperlynx creates the models of the board's traces and vias from your board files. You will run PCB translator to convert you board files to Boardsim. You will set up libraries to include your Xilinx parts and connector. You will specify the stackup data under Boardsim. If your simulation involves two boards inserted into a motherboard then you will want to run PCB translator on each (and stackup data for each) and set up a multiboard simulation.
Next you will have to select, from within the multiboard sim, your desired signal and export it to a free form schematic (LineSim) so that you can insert your Xilinx package parasitics block between the FPGA and the board traces. There are a few things you should do to the LineSim schematic and IBIS model at this point before you simulate that I will not go into here. Ultimately you will set up the IBIS-AMI model parameters from within LineSim and run the simulation.
Hope this gets you started.
thanks for your guidance.
the Virtex 5 GTP interface is CML.
I have downloaded the xilinx signal integrity simulation kit (ug351_v5_rio_sis_kit_2_0_beta_eldo.zip) from XILINX and mentor rocketIO simulation kit (HL_Xilinx_Kit_V_3_7_zip~) from mentor graphics for performing simulations of V5 GTP Transceivers but I am facing problems in integrating them. on executing the install file (Install_HypSisKit.exe), it asks for the xilinx kit, I am providing the path for the kit but it always says xilinx SISKIT not found. I guess some required folders are missing in the xilinx SISKIT due to which it is not getting integrated with the mentor rocketIO kit. what should I do now because mentor rocketIO kit won't work properly unless xilinx SISkit gets found.
plz help me in sorting out the actual problem.
I haven’t work with those kits recently, but from what I remember HL_Xilinx_Kit_V_3_7_zip is an old version (for HyperLynx 7.5) and I believe that is not for V5. I would suggest you reading the ug512 document that you can find in the ./docs sub-directory of the ug351_v5_rio_sis_kit_2_0_beta_eldo.zip. It contains detailed instructions about how to use this kit.