Is there anything else in the LVS rep that might give another clue? The part you showed does support the way OEN pin is connected to VDD in the source as you expected, but the layout OEN pin seems not connected to VDD for Xpad_A/B/C/D/E according to that part of the LVS report.
After double check, I am sure those "OEN" pin are all tied to VDD net! I really got confused.
Is there another discrepancy in the LVS report showing missing connections on the source side? That may provide a clue, can you show it here?
I found out the root cause! Actually, the LEF model of IO cell is NOT compliant with GDS. For LEF model, all metal layer on pin is visible while in gds view, top and top-1 metal is nothing!!! I asked foundry why, and was told full gds MUST be merged at foundry site, user can only get partial gds! Thus, I used top and top-1 metal to tie OEN to VDD when APR, but after gds merge, the OEN net is actually disconnected consequently.
I have one more question about "LVS BOX", I understood this option treats CELL as black box, only check port/pin connect to other circuit. But I found Calibre still extracts once layout exists. Would you advise?
Glad to hear about the cause. For the box question, you can control the netlisting of the devices in the box cells with this rule file statement:
LVS NETLIST BOX CONTENTS NO
(the default is YES)
Calibre creates the netlist contents by default. Even when the devices are inside the cell the LVS BOX statement causes Calibre to ignore the devices in the cell during LVS comparison so for LVS comparison phase it usually doesn't matter if the devices are in the box cells in the netlist or not.