Expert,

I used Micron's DDR3 IBIS model to simulate the clk signal.I found the .ebd modle which is given by the Micron don't have the location of the termination capacitance, CTT and the power up VDD.How can i add these in .ebd model?

Expert,

I used Micron's DDR3 IBIS model to simulate the clk signal.I found the .ebd modle which is given by the Micron don't have the location of the termination capacitance, CTT and the power up VDD.How can i add these in .ebd model?

There is an easy solution if you make one assumption. The termination resistors connect to a capacitor on the voltage side. Assume that the average voltage on the capacitor settles to VDD/2. This is a pretty good assumption because there is always one driver pulling up to VDD while the other pulls down to 0V. Then you can change the IBIS file, resistor_diff.ibs (attached) to have pullup resistors to VDD/2. With that little change, the complete net is included in the EBD and its associated IBIS files.

Weston

Hi Heoracle,

It is clearly mentioned in the readme file that for differential signal clk/clk# the terminator must be added externally.

You can extract this net to linesim and the you can add the termination.

Hope this will solve your problem

Regards,

Harish D