4 Replies Latest reply on Nov 28, 2012 12:03 PM by mugofgold

    need help with v2lvs utility


      Hello All,


      I have a few statements in my verilog file which were able to get converted properly in the spice format but some do not. I couldn't find much information from the help option either.


      Here are few details:


      INV U167 (.Y ( n155 ) , .A ( fs_dp_1kx10_1_l0_QB[5] ) , .VSS ( VSSC ) , .VDD ( VDDC ) ) ;

      --> v2lvs outputs as

                XU167 INV $PINS Y=n155 A=fs_dp_1kx10_1_l0_QB<5> VSS=VSSC VDD=VDDC ---> seems okay.


      But if I have few extra nets, it's not converting properly.


      .AB ( {n400 , n412 , ......, n401} ) ) ;

      --> v2lvs outputs as

                AB=n401 --> instead of AB[n]=n400 AB[n-1]=n412 ..... AB[0]=n401 (or in some other format..)


      Is there any option that I should choose to get the translation properly?