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Via simulation issue when translating from Allegro to Hyperlynx

Question asked by nptran on Jul 29, 2015
Latest reply on Jul 30, 2015 by nptran

Hi,

 

When I translate board file from Allegro to Hyperlynx. I use the via properties or visualizer in Hyperlynx boardsim. Via properties in Hyperlynx are very different from Allergor in terms of unused/unconnected with the via or pin, via impedance....

 

I have to study Insertion loss and return loss of differential signals using S parameter. I export S parameter including VIAs on transmission line but VIA is not correct.

 

Have you ever seen this issue?  Do you know how to translate correctly board from Allegro to Hyperlynx, in particularly the VIAS.

 

Thanks in advance for your help.

 

Nguyemn

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