2 Replies Latest reply on Jul 30, 2015 2:47 AM by nptran

Via simulation issue when translating from Allegro to Hyperlynx

nptran Sep 9, 2016 5:36 PM

Hi,

When I translate board file from Allegro to Hyperlynx. I use the via properties or visualizer in Hyperlynx boardsim. Via properties in Hyperlynx are very different from Allergor in terms of unused/unconnected with the via or pin, via impedance....

I have to study Insertion loss and return loss of differential signals using S parameter. I export S parameter including VIAs on transmission line but VIA is not correct.

Have you ever seen this issue? Do you know how to translate correctly board from Allegro to Hyperlynx, in particularly the VIAS.

Thanks in advance for your help.

Nguyemn

1. Re: Via simulation issue when translating from Allegro to Hyperlynx

matthias.cosaert Jul 30, 2015 12:18 AM (in response to nptran)

Not sure how it works in allegro but in Expedition PCB the pads are only removed when generating the gerbers/odb so they are also exported to the hyperlynx file.
But with hyperlynx 9.x you can toggle the removal of unused pads

MG581468:

HyperLynx v9.0 allows you to automatically remove the non-functional pads of all the vias in the design by selecting the Setup > Remove Non-Functional Pads menu pick.

When this command is invoked, all the pads will be removed EXCEPT the pads on the entry and exit layers and the pads on the outermost layers of the via (if different from the entry and exit layers of the via). The outermost layer pads are maintained to ensure the physical integrity of the signal via. This is a common practice in the manufacturing process.
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2. Re: Via simulation issue when translating from Allegro to Hyperlynx

nptran Jul 30, 2015 2:47 AM (in response to matthias.cosaert)

Hi,

Many thanks. I have successfully removed unused/unconnected with the via or pin.

Nguyen
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