Hi,
When I translate board file from Allegro to Hyperlynx. I use the via properties or visualizer in Hyperlynx boardsim. Via properties in Hyperlynx are very different from Allergor in terms of unused/unconnected with the via or pin, via impedance....
I have to study Insertion loss and return loss of differential signals using S parameter. I export S parameter including VIAs on transmission line but VIA is not correct.
Have you ever seen this issue? Do you know how to translate correctly board from Allegro to Hyperlynx, in particularly the VIAS.
Thanks in advance for your help.
Nguyemn
Not sure how it works in allegro but in Expedition PCB the pads are only removed when generating the gerbers/odb so they are also exported to the hyperlynx file.
But with hyperlynx 9.x you can toggle the removal of unused pads