Based on the screencapture, your layout has a DRC violation. The comment says that there is a shape on layer NWi that is in a "keep out" zone for the chip corner. Assuming you invoked Calibre RVE from your layout editor, and that you don't have RVE set to not change the view, the problem spot should be highlighted in the editor when you click the red number (then possibly the H in the tool bar) in RVE.
As to how to fix the DRC violation... well, you'll need to talk to someone familiar with the design. Usually the DRC rules are provided by the foundry and a group within the chip company.