I recently changed the net name delimiter from square brackets to none, in order to export a Cadence Allegro netlist.
Since then, several pull-up/down resistors connected to nets ripped from a bus or named as if they were fail drc-120.
Not all though, and in this example, one resistor passes drc-120, the other (highlighted net) fails.
So _SEL0 fails but _SEL1 passes (assuming it's related to the net name convention change...)
Anybody any idea what's happening here?