In DDR3 batch simulation results spreadsheet, some of the DQ signals are failing at monotonic at typical and more on slow edge rates. What changes need to do in the layout to fix the failures, what is causing non monotonic?
Although I have been working with LPDDR/LPDDR2 and DDR2 technology, I've seen monotonic errors due to the drive strength differences between slow/typical/fast process corners. I take it you are not seeing these problems in the fast condition?
Are any of the T-line characteristics drastically different on the nets that are showing failures? Note any major differences (net length, termination lengths, ect).
Where is your measurement point? Die or the pin? Depending on the T-line characteristics; you can see a rather large reflection caused from the T-line impedance and the package RLC to the die. Try measuring at the die and see how things change. In my opinion, how the signal looks at the die is most critical since that is where the data is being latched. You can't ignore the package parasitics when looking at SI and timing.
Hope this helps.
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