Is there a method in the DDR controller timing model to perform per byte lane DQS shifts?
Yes, you can do this in the DDRx Wizard.
Enable "Data Timing (Read only)" and "Clock to strobe skew timing" from Nets to Simulate page.
Enable some data nets in the Disable Nets page.
Make sure write leveling page table is empty and Use DDR3 Delays File if available is off.
This will create the DDR3Delays_autogenerated.txt with some initial delays for each DQ and DQS nets which will minimize the (Average Setup Time – Average Hold Time).
Now rerun the simulation for read with the option Use DDR3 Delays File if available on.
You should now see the difference in results with more balanced margins for setup and hold.
This support has been improved in 9.0 and we will document these procedures in details in TechNotes.
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