7 Replies Latest reply on Jun 4, 2013 9:02 AM by Stone

    Hierarchical Design


      Hi All,


      I am wondering, how to create a hierarchical design, where I do have 2 or more pages referred to by the upper block.

      So my first question is: Can DXD handle 2 or more sheets (schematcis pages) within one hierarchical block?


      If so - the question is what happens to signals - and their names - which connect 2 pins on symbols on different pages within this hierarchical block, when using this block 2 or more times? How can DXD seperate those inter-sheet signals, when only the signals going in- and out of the hierarchy are shown in the block?


      Thanks in advance,



        • 1. Re: Hierarchical Design

          DxDesigner can handle any number of pages at any level of hierarchy. If you instantiate the hierachical block twice then the nets are flattened based on the nets at the top level, so in the example below aBlock is used twice and has pins A and B. In the first instance nets A and B connect to the pins and propagate down to the corresponding pins in the block (which are A and B based on the pin name). In the second instance nets C and D connect to nets A and B in the lower level schematic and when the schematic is used in layout nets A,B,C and D will be passed through to layout, so the second instance of the block effectively has the nets renamed to C and D.

          • 2. Re: Hierarchical Design

            To answer your second question, inter-sheet nets are also made unique when creating a PCB netlist by pre-pending with the block instance ID ensuring nets only connect to related parts.

            • 3. Re: Hierarchical Design

              Hi Robert,


              Thanks so much for the quick answers.

              So when the netlist tool of Expedition is adding prefixes to those signals - it makes it more difficult to find those nets in the CES - and also within the layout - or Hyperlynx.

              Can you configure the handling of those signals within the tool?





              • 4. Re: Hierarchical Design

                CES sees the flat net (top net name). And no you can't configure this.

                • 5. Re: Hierarchical Design

                  So that is the problem: I cannot find the signal  - lats call it RX_IO1_TO_IO2, since it only goes from page 1 to 3 of that hierarchical block. Meaning I cannot distinguish between the RX_IO1_TO_IO2 in one instanciation from the RX_IO1_TO_IO2 in the other instanciation? - Is that right?

                  • 6. Re: Hierarchical Design

                    Just checked this and it adds a suffix to the nets that traverse sheets, but CES will cross-probe to the right instance. My guess is you want some further control over this, in which case you should look at posting something on the Ideas pages to enhance the functionality.

                    • 7. Re: Hierarchical Design

                      Thanks for checking -.- didn't have a chance yet to test it myself.

                      So if the tool adds a suffix - that would be okay. Then I should be able to see it in my netlist too.

                      I think I will try to make a simplke designm and tets it myself - the I see if that works for me or not.


                      Thanks so much Robert - really appreciate it!