I don't know about Verilog -- shouldn't that come from Virtuoso's stream out? -- but if you are using Calibre xRC or Calibre xACT you can get not just a SPEF netlist, but one set up for PrimeTime.
In Calibre Interactive - PEX, click the Outputs button, then select the Netlist tab. You set it for SPEF output in the Format dropdown. At the very bottom of that dropdown, according to the 2013.3 manual, there is also a checkbox for the PRIMETIME keyword. (I usually use batch mode, so cannot tell you how far back these instructions are valid for.)
If you aren't sure how to set up a Calibre Interactive run, the xRC manual has a chapter walking you through the basics, or you can refer to the Calibre Interactive manual, which has a chapter on PEX specifically. (And also a chapter on integrating Calibre Interactive into Virtuoso.)
Hope this helped-
Still some questions:
1. Should that the SPEF extraction for a standard cell based digital circuit be excuted using gate-level extraction?
2. Can the STA result based on SPEF from Calibre be used to sign-off?
1. If you are extracting only the standard cell, you should probably do flat extraction. If you are doing a design with standard cells, gate-level is a better fit -- but you will need models to provide cell values for STA. (Gate-level extraction is just the portion of the design outside the cells listed in the xcell list; for many designs, that's interconnect and some glue logic.)
2. Whether it can be used for sign-off depends on the foundry's requirements. I know of no technical reason it cannot be used, but my experience was with larger (>90 nm) process nodes. I believe Mentor acquired Pextra (the source for the current Calibre Xact) because it was developed specifically for the extra requirements of small nodes. Check with the group who will be doing the manufacturing what they require for sign-off qualification.