Using Calibre to generate Verilog netlist and SPEF file PrimeTime

Discussion created by liyuanqing on Nov 14, 2013
Latest reply on Nov 18, 2013 by samantha_lizak



I now have a layout containing stadard cells in Cadence Virtuoso, and want to generate a Verilog netlist of this layout and an SPEF file to excute STA for this design using PrimeTime.


Can Calibre offer the Verilog netlist and SPEF file? If it can, how can I get these?