Hopefully the long title is not to off-putting. Some of our team members are having difficulty understanding the connectivity in a design which includes repeated hierarchical blocks. Some of the blocks are microprocessors, and due to the large number of I/O, we need to use busses to connect signals through the hierarchy. Because of the repeated blocks, we have generic netnames at the lower level, such as GPIO1, GPIO2, etc. As the signals traverse upward, they take on unique, specific functions, such as PROC1_PS_ENABLE, or PROC2_LIMIT_SWITCH_SENSE. These nets are elements of busses that exist at the various levels.
One of our software developers noted that from reading the exported pdf, there's no way to know which pin of a particular processor connects to which upper-level function, because the netnames are aliased to the elements of the upper-level bus. I can supply the quick connection view output to him, or the busconts.ini file, for that matter, but it does raise an interesting question. In an environment in which people have long been accustomed to getting all netlist information from a (flat) schematic, is there a solution that satisfies this need for hierarchical schematics?
Thanks in advance,