I know there are several discussions on this topic but I can't find a similar one to the test we made.
We wanted to create a kind of assignment table for the IO signals of our CPU. There you can see the connection of all the nets from the different hierarchical IO blocks to the CPU nets on one single page (see short example image below). This is extremely helpful for our software programmers.
As you can see there is a hierarchical block in between which connects two nets together like In1 <> Out1. In the block the two nets are shorted by a direct connection between the IN and OUT port (see following picture).
By testing this in Expedition I know this works for EE7.9.5 Update 6. But I'm not sure if this "hack" is allowed and if there are any side-effects I didn't realize. Futhermore I don't know if this will be possible in future releases of EE. Do you experts have any advice for us or other solutions to solve this issue?
Many thanks in advance,