Nothing is wrong, you just have overdrived. If you check the driver's rise/fall waves, you will find sum of Tr and Tf is larger than 1/f(125M). so you have to t decreas frequency to a reasonable value(l/f > Tr+Tf) for avoiding overdriving. Maybe it's better that a simulator have capability to check overdriving before run simulation.
Controller datasheet speicfies frequency upto 180 Mhz but IBIS model doesn't support this.
I am doing prelayout simulation for 120 Mhz.to decide maximum allowed length for address/data line to drive SDRAM and FLASH.
Driving at low frequency will give incorrect result
How can I decide the length above which signal will have issue.
If you use DDR2 2T timing mode, Address frequncy is half of the clock frequency. For 180MHz Clock, youronly need to simulate at 90MHz for address.
IBIS model supplied by manufacrurer is having an issue. Reply from IBIS vendor.
This part has changed since it was originally modeled back in 2011. The original datasheet called out a single drive strength for the I/O pins, the new datasheet has two drive strength.