Please let me know if the centre to centre distance of DC blocking caps of differential signals is critical or not.
The distance between two dc-blocing capacitors is mainly dertermined by follow factors:
1 the spacing of differantial pair
2 capacitor case size(width)
On the cases where capacitor's width is larger than the spacing of differpair, you have to spread the spacing(covergence segments). Althoug the convergence lenght normally less than 2 mm, it's better to simulate this convergence segment using 3D Tools such as Hyperlynx 3D EM if data bit ups to 10Gbps.
Many thanks for your answer.
Please confirm my understanding: the smaller the differential pair covergence segments, the better.
Literally speaking, it"s better to achieve shortest covergence segment length. However, the convergence isn't only thing that constributes to channel performance. That's why you need to do simulation and need a 3D extractor to do trade offs during design process.
We are working on PCIE TX channel.
Please check the response from a guy who is using another SI tool:
"The Caps should be considered as a microstrip transmission line differential pair, where width, thickness, distance to ground and distance between the caps defines the impedance. Reducing the spacing lowers the effective differential impedance. "
He suggested use 35mil distance for 0201 size cap.
But his idea is opposite to your suggestions.
You SI guy have misunderstand something. If he wish to get inside what a MLCC behavior over widegband, you can suggest he take a 3D EM tool to build the caps and do simulation. yanfeng
How do you think if we make a cutout under each DC blocking caps to improve impedance mismatch?
For microwave application, it's common practice to do cutoff underneath reference plane of the cap, to eliminate parasitic capacitances between the capacitor body and refenrence plane. Recently, there are many digital desingers also like to do cutoff for DC-blocking capacitor in GHz serial channle, think it will be helpful to get a smoothful impedence transition while signal from microtrip/strip goes into the capacitor terminal and versa.
Just as you known, thouse monolithic microwave cap is only be 2-30pf and very sensitive to plane, so cutoff is a must. However, for blocking cap which be in 0.01uf-0.1 uf is MLCC type, 10% tolence, but the parastic capacitance introduced by the coupling between body and ground is very very tiny, so a smooth impedence is the only thing you may hope to get from cutoff in the reference ground.BTW, We also have done some simulations and measuments for studing cutof's effectness and conclution is that there is no observable effectnetss up to 10GBps.
1) try to get precision model for your blocking cap. you can measure it by youself or from vendors
2) do cutoff because it have no cost if you like but please keep this cutoff small
3) do simulation for concepthd proof. There are excellent EM tool for deal with this and very good circuit analysis tool to support full channel simulation.
Mentor will hold a webnar of Modeling Signal Discontinuities in SERDES Channel at January 22. you and your si guy may take this seminar and ask your question there.
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