Is there currently any available method to Check for symbols with a non desired "forward to pcb" state or change?
I dont see anything in the verify or DRC checks.
A user creates a local symbol and changes the state to False, so they can package with a partial amount of the components etc?
Later on if the user forgets or resources change, we need some method to understand which parts are being skipped during packaging etc.
A users accidentially changes a state of a symbol to false etc. (Currently you can change any symbol via properites)
Within DC it was 100% or nothing and most Engineering users hated this fact. Although I like the ability
of compiling and not holding users to the same standard, it would be optimal to be able to check these.