4 Replies Latest reply on Oct 9, 2014 6:42 AM by agxinmj

    xilinx sstl15 ibis doesn't meet micron ddr3

    xilinx.moshi

      I'm simulating a circuit with virtex-6 fpga and micron ddr3, the problem is the sstl15_dci_o standard in xilinx ibis doesn't meet the vcross_high and vcross_low in the micron  ibis. so when i connect these two, I always get a failed "differential crossover limits" for my dqs signal.

      can anyone help me please?

        • 1. Re: xilinx sstl15 ibis doesn't meet micron ddr3
          xilinx.moshi

          here is what I've done:

          the simulation circuit is like this:3.jpg

          and when i simulate the whole board with ddr3 batch simulation it will end with something like this in the end for the SI measurements:

          6.jpg

          so I've decided to connect virtex-6 pins directly to the 40 ohm termination to see the output waveform:

          1.jpg

          but even in this topology the fpga's sstl15_dci_o will have the following output, and hence the crossover is not in the range of micron specified ( 0.575 to 00.925 volts)

           

          4.jpg

          even the output is not symmetrical. but when i connect two micron's ddr3s the output wave form will be something like this:

          5.jpg

          which is symmetrical and the cross over is in the range of vcross_low and vcross_high ( 0.575 to 00.925 volts)

          • 2. Re: xilinx sstl15 ibis doesn't meet micron ddr3
            agxinmj

            hai

             

            can you provide the ibis model ?

            the ibis model contains submodel selector for termination schemes

            due to some wrong source termination scheme selected in the model  the wave form appears such

            select the driver and select the model selector select as output at driver end and input at the receiver end

            select the sub model and assign the sub model which has some termination ODT defined init ,with the clocking speed

            regards

            AGXIN.J

            • 3. Re: xilinx sstl15 ibis doesn't meet micron ddr3
              agxinmj

              Hai

                       if the high and low threshold  of the wave form appears  correct and only the levels marked in the dotted line is alone wrong then select the icon in the bottom

              peak to peak.....undershoot overshoot......at last there will be an icon for selecting high low threshold for appropriate ddr defined in your model

              regards

              AGXIN.J

              • 4. Re: xilinx sstl15 ibis doesn't meet micron ddr3
                agxinmj

                Hai

                           there are some issues with your stack up also the layer impedance is very low

                may i know you are doing line sim or board sim

                the differential pairs are coupled segments but your segments appear to be uncoupled

                regards

                agxin.j