This is an attempt to use a different forum than the ideas page to make a plea to Mentor graphics to improve its products. This is also an attempt to gather opinions on the matter, in the hope that I'm not alone.
Since transitioning to PADS in July of 2013, and using it for over a year now, one major issue that I've observed is the lack of component based rules in PADs Layout. With the recent release of the document "BSD Release Information by Product," which states the planned feature release for PADs into 2015, component based rules in Layout is a feature that is absent from this list. This is a feature that has been mentioned on these forums, and the "idea" that Layout should observe component rules has been posted on the ideas page since 2008 (idea D372, which was moved to out of scope without any explanation), including an idea posted by myself (D13459).
However, I would argue that Layout's lack of component rules is more than just fodder for an idea, but a flaw in both the program and its integration with Router. While SMD components become smaller and push clearances tighter and tighter, designers like me don't necessarily want the SMD components to dictate the default clearance and spacing. This works very well in Router. I can have larger default rules to maintain manufacturability and integrity, while reducing the clearance rules on the component level to route from SMD components (QFPs, QFNs, BGAs, etc). What happens is when you perform your final DRC checks in Layout, the tighter component rules are not recognized, and seen as violations of the defined constraints.
Why is this a problem? As a design engineer, I rely upon PADs to be rules based to make sure my design is electrically correct and manufacturable. I rely upon the design verification to tell me in a concise easy to decipher way where problems lie. When I run my final verification in Layout, I will get an obscene amount (764 in my current design) of DRC errors which are false because Layout ignores component based rules defined in Router. For example, every pin on a QFP I will get an error, so a 144 pin QFP will create 144 errors. At this point, the tools are broken. I cannot rely on the tools to accurately tell me what problems exist with my design. At this point the onus is on the user (me) to manually sift through the errors to identify which errors are real, and which are falsely reported because Layout will not recognize component level rules. The point of purchasing the tools in the first place is to not have to manually verify rules like this. This is both a time consuming process, and an error prone process since the ability to sort errors by type in Layout does not exist. So, for instance, in my current design I have 764 errors caused by Layout ignoring component level rules, and there is a great possibility that a real error is buried in the stack, and I'll miss it.
So this is a both a question and a plea. Mentor Graphics, how do you not see this as a problem? Mentor Graphics, please correct this. Layout software packages are supposed to be rules based. And without a reliable and trust-able approach to how rules are defined and handled, it is hard to trust the software and rely upon it.