I am working on a layout and am encountering a strange problem with extraction. I have passed LVS checks in LVS and PEX. My PEX run finishes without errors or warnings, but within the calibre view schematic,the transistors are floating. I am not sure if this is a problem related to the the PDK (TSMC) or if I have some setting incorrect.
I am hoping someone might have a solution to this problem.
The transistors may not be floating. What you can do is query the pin, and see the node name. Then somewhere else, say on a parasitic resistor, there should be the same node name. The main question is, when you run simulation with the calibreview, is everything connected up, and are you seeing simulation results that are expected?