6 Replies Latest reply on Nov 4, 2015 9:29 PM by conviction

    Cycle-to-cycle Jitter measurement of a Delay-Locked Loop

    conviction

      Hi All,

      Anyone can guide me to the number of cycles required to run Transient analysis in order to measure an accurate value of the cycle-to-cycle RMS jitter of the output signal of a Delay-Locked Loop circuit using Mentor Graphics software using EZwave 13.2d version?,

      In other words, what is the STOP Time required in the Transient analysis to get an accurate value of the jitter?

      Should I run Monte-Carlo simulation also for the same jitter measurement?

      Appreciate your help! Thanks in advance!.

        • 1. Re: Cycle-to-cycle Jitter measurement of a Delay-Locked Loop
          farshad_dailami

          Your transient simulation time depends on the the settling time of your PLL circuit. You can look up how to calculate a PLL settling time. This will be a decent estimate, as your actual simulation result (with full transistor models) will vary. Set your ending simulation time for something larger than this estimate.

           

          You can and should perform some sort of corner or M-C simulation to see where your performance extremes may be. Depending on who you consult, some engineers prefer all-corner simulations while other prefer random corner or Monte-Carlo. My personal take is that you need a combination of both. That is, you should select and simulate your extreme process corners (WCP, WCS, WC0, WC1, TYP) with associated power and temperature extremes. This will give you one set of data. You can also set up a Monte-Carlo scenario where you randomize the process/power/temp variables and get more coverage in your simulation space. With these data sets combined, you should be able to get a good feel for your circuit's performance.

           

          Hope this is helpful.

          • 2. Re: Cycle-to-cycle Jitter measurement of a Delay-Locked Loop
            conviction

            Thank you so much farshad_dailami.

            Actually, my circuit is DLL, but I think the operation is somehow similar to that of the PLL. For the settling time, I think you may mean "the locking time" as it is the time required by the PLL or DLL to realize a stable state, if I am not mistaken.

             

            Regards!

            • 3. Re: Cycle-to-cycle Jitter measurement of a Delay-Locked Loop
              farshad_dailami

              Yes, DLL and PLL circuits are similar in operation principle; and, settling time is interchangeable with locking time. Basically, the circuit must have achieved a stable lock.

               

              fd

              • 4. Re: Cycle-to-cycle Jitter measurement of a Delay-Locked Loop
                conviction

                So, for example, if the locking time is 100 cycles, this means that the Transient analysis time (STOP TIME) should be set to 100 cycles?

                and accordingly the time for the M-C and PVT corners?

                • 5. Re: Cycle-to-cycle Jitter measurement of a Delay-Locked Loop
                  farshad_dailami

                  A minimum of 100 cycles. I would overshoot by maybe 5% to 10% to ensure that what you measure does not include any period variation from the output transient results (so 105 to 110 cycles). That is, make sure you're not seeing any variation in the period for a few cycles. Does that make sense?

                   

                  For example: Let's say you've calculated that the lock time is 100 nSec. Set the simulation time to 105 to 110 nSec. Look at the results and see if your measurements are consistent.

                   

                  Play with the simulation time until you're satisfied that the output is completely settled. What happens as you vary corners is that the period will vary (as expected). You will want to capture enough cycles to make sure you have an accurate measure of this change over corners.

                   

                  Hope that makes sense.

                   

                  fd

                  • 6. Re: Cycle-to-cycle Jitter measurement of a Delay-Locked Loop
                    conviction

                    Thank you so much Mr. farshad_dailami for your reply and assistance.

                    I think that can help a lot.

                     

                    Regards!