i have just realize that TI choose to not giving their DDR controllers AC timing specifications. Their IDEA is to provide customers a series of rules and constraints to follow and... that's it.
As an SI engineer, of course, i am not happy, of this kind of approach.
Furthermore they give me a link to their blog where TI support are saying to customers that Hyperlynx+IBIS models are not good for judging timing margins.
I don't think that what they are saying and their conclusions are correct. I think also that there is a very tight link between SI and Timing analysis. I would really appreciated your thought on this matter.
This is the link to the TI public BLOG discussion: https://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/327845