I have an analog design and i am trying to extract the parasitics to do the post layout simulations. As the design is big, doing a transistor level extraction with "R+C+CC" takes time and yields a huge netlist which again takes a lot of time to simulate. My aim is to reduce the number of nets in the extracted list and so I want to do selected extraction.
I have the following 5 cells(four instances of "Stacked_cell_2_3" and one instance of "current_dac") in my layout and schematic for which I want to do only "R" type of extraction. To do so, from Calibre GUI I first generate just the PHDB, after that I create PDB multiple times with different nets and type of extractions. Finally I create the netlist.
Now, when in the top level nets i provide "XI21/?" or "XI11/?", it works fine. In the transcript I can see that all the nets of instance XI21 are selected for extraction. However, when I provide "XI22/?" or "XI12/?" or "XI10/?", I get the following error
WARNING: Cannot include toplevel net XI22/?. Names(s) not found in source.
FATAL ERROR: None of the specified nets was found.
excerpt from the source Netlist:
XI21 VSS Vd_4 Vdd Vg1 / Stacked_cell_2_3
XI11 VSS Vd_4 Vdd Vg1 / Stacked_cell_2_3
XI22 VSS Vd_4 Vdd Vg1 / Stacked_cell_2_3
XI12 VSS Vd_4 Vdd Vg1 / Stacked_cell_2_3
XI10 TX_PAD_PA_bc_b0 TX_PAD_PA_bc_b1 TX_PAD_PA_bc_b2 VSS TX_PAD_PA_Iref op1 Vdd_1 / current_dac