6 Replies Latest reply on Jun 4, 2010 8:38 AM by chris_balcom

    Unable to use LEFDEF as input to do LVS

    kenny.lee

      I follow the guideline specified in the calibre manual to setup my LVS rule file to use LEFDEF as input ,

      but I awlays got empty-pin in SUBCKT of sub-circuit in layout.spi (check from "calibre -spice layout.spi"), showing as below

      How can I do ?

       

      0. all_tech_layer.map

      M1                 drawing          1 0
      M2                 drawing          2 0
      M3                 drawing          3 0
      M4                 drawing          4 0
      M5                 drawing          5 0
      M6                 drawing          6 0
      M7                 drawing          7 0
      M8                 drawing          8 0
      M9                 drawing          9 0

      AP                 drawing          10 0

      VIA1               drawing          11 0
      VIA2               drawing          12 0
      VIA3               drawing          13 0
      VIA4               drawing          14 0
      VIA5               drawing          15 0
      VIA6               drawing          16 0
      VIA7               drawing          17 0
      VIA8               drawing          18 0
      RV                 drawing          19 0

       

      1. setenv MGC_CALIBRE_DB_READ_OPTIONS "-layerMap all_tech_layer.map -annotateNets TEXT ALL -annotatePins TEXT"

       

      2. LVS rule file :

      PRECISION 2000
      LAYOUT PRIMARY "TOP"
      LAYOUT PATH "try_lefdeflvs.lef" "try_lefdeflvs.def"
      LAYOUT SYSTEM LEFDEF

      SOURCE PRIMARY "TOP"
      SOURCE PATH "try_lefdeflvs.spi"
      SOURCE SYSTEM SPICE
      HCELL CELL_A CELL_A

      HCELL CELL_B CELL_B

      LVS BOX CELLA CELLB

      ...

       

      3.perform LVS command

         calibre -lvs -spice layout.spi -hier  Calibre_LVS_Rule_file

       

      4.Results of layout.spi

      .SUBCKT CELL_A                     < -- Empty-pin definition
      ** N=6 EP=0 IP=0 FDC=0
      .ENDS
      ***************************************
      .SUBCKT GUC_CELL_B         < -- Empty-pin definition
      ** N=8 EP=0 IP=0 FDC=0
      .ENDS
      ***************************************
      .SUBCKT TOP
      ** N=10 EP=0 IP=958 FDC=0
      X931 CELL_A $T=186800 200800 1 0 $X=186800 $Y=195160
      X932 CELL_B $T=195200 190720 1 0 $X=195200 $Y=185080
      .ENDS

        • 1. Re: Unable to use LEFDEF as input to do LVS
          chris_balcom

          Missing pins for LVS BOX cells are usually caused by text problems. I didn't see any text layers mentioned in the layer mapping, that could be a problem.

           

          Missing pins for HCELL's are usually caused by lack of connections from devices inside the hcell to devices outside the hcell. I didn't see any device layers in the layer mapping, that could be a problem too.

           

          There were statements there for HCELL CELL_A (with an underscore) but then another statement for LVS BOX CELLA (without an underscore) and the example subcircuit showed CELL_A with the underscore. With those in mind, I wasn't sure if there were typo's or maybe both forms existed intentionally.

           

          Here's a link to a TechNote on Supportnet that discusses LVS BOX missing pin problems:

           

          http://supportnet.mentor.com/reference/technotes/public/technote.cfm?tn=MG16677

           

          It might be interesting to see if you get the results you want with gds format, just to test the flow in a different way. It may help determine if the SVRF statements for connectivity extraction are a problem with this design, or if the lefdef is actually the problem.

          • 2. Re: Unable to use LEFDEF as input to do LVS
            rn

            Hi Chris,

             

            When performing parasitic extraction with LVS BOX, or black box in general, the results do not include the sub-circuit/instances of these LVS/black boxes in the extracted netlist. Where these black boxes should have been are now empty spaces. I always had to add these LVS box instances manually after the extraction. This is often very tedious for large circuits with many of these instances. I'm not sure if this is true in general or just specific to my PDK (I'm using a parasitic tool called PLS which relies on starxtract from synopsys)

             

            Is there a way to systematically tell the tool to also include these black-box instances inside the extracted net-list where they should be? I tried many different ways but to no avail except manual insertion.

             

            Thanks,

             

            RN.

            • 3. Re: Unable to use LEFDEF as input to do LVS
              chris_balcom

              Hi RN,

               

              I'd like to know if the LVS BOX cells are missing from the initial connectivity extraction results. Do the LVS BOX cells appear as empty subcircuits, where they belong, in the initial netlist extracted from "calibre -spice" ?

               

              It should be easy for us to force automatic creation of these cells during "calibre -spice" hierarchical connectivity extraction. There are just a few requirements to make that happen.

               

              If they do exist at this early stage, then are missing later in a flow, we probably need advice from someone else. If they're missing during the initial hierarchical connectivity extraction when GDS format is used as the input, it should be easy for me to help you fix that.

               

              So for me, the two interesting questions at this point are:

               

                   1. Is it a problem at "calibre -spice" ?

               

                   2. Is the input format GDS or LEF/DEF ?

              • 4. Re: Unable to use LEFDEF as input to do LVS
                rn

                Hi Chris,

                 

                Thanks for the prompt reply. I really appreciate your response.

                 

                The input is GDS format.

                 

                Let me re-iterate what you said. When performing an extraction, this tool does LVS first, and the resulting netlist does have the empty subcircuits with just the pin definition of these LVS black boxes. So, i guess that the answer to your question is yes, it does place these empty subcircuits during the initial calibre -spice hierarchical connectivity extraction.

                 

                however, once this step is completed, the extraction begins. This step outputs a netlist with all the parasitics and everything else except the LVS black box that we declared. The net names still match the initial circuit though, and so it was possible for me to manually place these cells in once the extraction is done. However, this is only possible with just a few cells.

                 

                Is this something that we can fix?

                 

                Thanks,

                 

                RN.

                • 5. Re: Unable to use LEFDEF as input to do LVS
                  chris_balcom

                  Hi RN,

                   

                  That's good information. Now I see the problem appears to be later in the flow, closer to the parasitic extraction side of things. What extraction tool or flow are you using? I think we need to get someone in the conversation that is familiar with your extraction tool flow.

                  • 6. Re: Unable to use LEFDEF as input to do LVS
                    chris_balcom

                    Hi Rn,

                     

                    One other question... You mentioned the LVS extracted netlist contains the black boxes with pin definitions. Does that mean the pins aren'ty missing anymore, as in the original problem at the top of this thread? Maybe the original problem was: "LVS BOX cells don't have any pins". And the new problem is "LVS BOX cells are created during LVS but dropped during parasitic extraction flow"?