I am attempting to export a verilog netlist from a schematic in Pyxis 10.5.4. The schematic is very simple and only contains symbols which themselves have their own verilog netlists. When attempting the export, I get the following error (amongst other similar errors):
*** error *** : The default model selection 'VERILOG=verilog' cannot be found in an NCF.
The closest matching NCF item is 'SYMBOL'. Line: 4 File: /opt/mentor/tutorial/Pyxis_SPTfirstname.lastname@example.org/nmos.ncf
This is because the netlister is diving down below the symbol's netlist and looking at the devices that make up the circuit which the symbol is representing. How do I tell the netlister to stop at a level at which there is a verilog representation of a circuit?