1 Reply Latest reply on Aug 4, 2016 10:00 PM by agxinmj

    DDR4 model selection while simulating ADDRESS signal

    9dc1212f-cb89-8a24-0100-014e727abccf

      As there is fly-by topology used in DDR4 address, command and control signals. I am doing address line signal integrity, as address line have I/O logic as SSTL12. But in ibis model it comes as three variants as SSTL12, SSTL12_CLASS1, SSTL12_CLASS2.

      What variant should i use whether simple SSTL12, class 1 or class 2.

      Please help me out of this and provide valuable inputs.