AnsweredAssumed Answered


Question asked by on Aug 16, 2016
Latest reply on Aug 22, 2016 by dan_liddell

Hello Everyone,


I'm working on the LVS of a block and I'm facing the below issue.


LVS is resulting in INCORRECT due to 'Different number of ports' between the layout and schematic . This is due to an issue occurring at the connectivity extraction stage.


Extraction Report Warning:

WARNING: Top level port name "A" on net 2 at location (72.556,421.3) already used on net 1; ignored.


LVS Report:


                                   INCORRECT NETS

DISC#  LAYOUT NAME                                               SOURCE NAME


  1    Net A                                                     ** no similar net **



Clear Picture:

In the layout , there is a Macro, and one of its pins, Q[65], is connected to the 'A' pin of a standard cell (buffer), the 'net2' in the above warning is this net. The 'net1' in the above warning is another net, connecting another one of the macro's pins, Q[67] , to another buffer's 'A' pin.


Now Calibre is discarding one of these 'ports' causing the above error with different number of ports in layout than in the source (I'm not sure about this!). Why is Calibre treating the input pins of the standard cells (A pin in this case) as a common pin? Both the nets in the question have unique names in the layout, Calibre is considering the 'A' pins in both the cases as a common pin (Kindly correct me if I'm wrong)



How do I fix this? Any help would be greatly appreciated.