1 Reply Latest reply on Aug 22, 2016 10:15 AM by dan_liddell

    LVS EXTRACTION ERROR

    jijesh.kunnath@nxp.com

      Hello Everyone,

       

      I'm working on the LVS of a block and I'm facing the below issue.

       

      LVS is resulting in INCORRECT due to 'Different number of ports' between the layout and schematic . This is due to an issue occurring at the connectivity extraction stage.

       

      Extraction Report Warning:

      WARNING: Top level port name "A" on net 2 at location (72.556,421.3) already used on net 1; ignored.

       

      LVS Report:

      **************************************************************************************************************

                                         INCORRECT NETS

      DISC#  LAYOUT NAME                                               SOURCE NAME

      *************************************************************************************************************

        1    Net A                                                     ** no similar net **

       

       

      Clear Picture:

      In the layout , there is a Macro, and one of its pins, Q[65], is connected to the 'A' pin of a standard cell (buffer), the 'net2' in the above warning is this net. The 'net1' in the above warning is another net, connecting another one of the macro's pins, Q[67] , to another buffer's 'A' pin.

       

      Now Calibre is discarding one of these 'ports' causing the above error with different number of ports in layout than in the source (I'm not sure about this!). Why is Calibre treating the input pins of the standard cells (A pin in this case) as a common pin? Both the nets in the question have unique names in the layout, Calibre is considering the 'A' pins in both the cases as a common pin (Kindly correct me if I'm wrong)

       

      lvs1.PNG

      How do I fix this? Any help would be greatly appreciated.

       

      Thanks,

      JK.

        • 1. Re: LVS EXTRACTION ERROR
          dan_liddell

          Hi,

           

          From the SVRF Manual, "LVS Circuit Extraction Messages" section:

           

          WARNING: Top level port name “<name>” on net <id> at location (x,y) already used on net <id>; ignored.

           

          This warning indicates a top-level port naming conflict in the hierarchical SPICE netlister. This occurs when two or more nets are connected to top-level-cell ports with identical names. The warning appears only when the port names would have been otherwise used for netlisting. Specifically, the two nets in question must be unnamed or must have names that are not valid for netlisting, and the port name must be valid for netlisting. The hierarchical SPICE netlister uses the port name to identify one of the nets and its port, and uses the internal number of the other net to identify that net and its port. The net that receives the port name is chosen arbitrarily. This message occurs when LVS Netlist Connect Port Names YES is specified.

           

          Your rule file specifies that this situation be flagged with a warning. There are two choices to rectify it. 1) Set LVS Netlist Connect Port Names NO (the default). 2) Name the nets differently that give the port names.

           

          dan