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How do I "overlap" vias with testpoints. 

Question asked by passion4pcbdesign on Oct 11, 2016
Latest reply on Oct 19, 2016 by passion4pcbdesign

The testpoints are only on the bottom side.  The company does not want to use vias for testpoints, nor do they want to have a trace go from a via to a test point (antennas).  I have been instructed to have the edge of my test point be adjacent to the via hole (not the pad).  How do I set a zero clearance for vias and test points?  The via is either sucked to the center of the testpoint or I get immovable metal object errors.