4 Replies Latest reply on Oct 19, 2016 6:08 AM by passion4pcbdesign

    How do I "overlap" vias with testpoints. 

    passion4pcbdesign

      The testpoints are only on the bottom side.  The company does not want to use vias for testpoints, nor do they want to have a trace go from a via to a test point (antennas).  I have been instructed to have the edge of my test point be adjacent to the via hole (not the pad).  How do I set a zero clearance for vias and test points?  The via is either sucked to the center of the testpoint or I get immovable metal object errors.

        • 1. Re: How do I "overlap" vias with testpoints. 
          greg.hall

          I haven't tried any of this, but it is an idea that I think may resolve your problem.

          1st Define your test point pad as an oval shape with an offset origin (similar to sketch included)

          2nd Then on your design if you place this oval test pad onto a via, it will locate at the cell origin.

          Via will be attached to the test pad with no track and can be probed onto left hand side of test pad - so not as to probe direct onto a via.

          • 2. Re: How do I "overlap" vias with testpoints. 
            matthias.cosaert

            You can allow vias under the pad in the editor control but you should create a unique pad in the padstackeditor for testpoints just in case same pad is used on SMD components to avoid accidental vias in them. (can also place a via obstruct in center on the cell)


            Though for some reason it does not allow to place the testpoint with an offset on the vias but it does work if you place the testpad next to the via, route a trace and then move the testpoint onto the via... (or place with drc off)

             

            Working with offset pads seems a bit dicy because the testpoint center to center will not be chekced properly when using different rotations and not sure if all downstream tooling will use pad center and not testpoint part coordinates.

            • 3. Re: How do I "overlap" vias with testpoints. 
              raliesch

              if i wannt to place a Via in the Testpoint pad, you Need to make sure you go to Padentry in the Editor Control Routetab. Select the Pad from the Testpoint and set the flag "Allow via Under Pad" and if you wannt this "Allow off Pad origin".

               

              This is what i need to do, may it is helpfull to you.

              BR

               

              • 4. Re: How do I "overlap" vias with testpoints. 
                passion4pcbdesign

                Thanks, I appreciate both responses.  Both of you have been more than helpful.