7 Replies Latest reply on Nov 8, 2016 10:47 AM by lanelone

    xDX FPGA IOPT workflow in VX.2

    lanelone

      There are two ways how to use the IOPT for FPGAs.  Either generate all symbols in the IOPT tool and add it to schematic or use symbols created in Library Tools (Symbol Editor or FPGA part wizard) and import it to the IOPT. I would like to slightly modify symbols for schematic. Generated symbols are too large, they do not even fit to A3 schematic sheets in some cases. Also the embedded symbol editor in the IOPT is very limited compared to fully fledged xDX Symbol Editor if you want to add properties.  In the VX.2 symbols are automatically converted to a compound symbol after editing, but there compound symbols are not recognized by the IOPT ( logic error in symbol file - unrecognized construction at line .... errors).

      Is it possible to edit symbols in xDX Symbol Editor (rearrange pins, switch pin orientation, etc.) and still be able to to optimize FPGA pinout in the IOPT?

      Thanks

        • 1. Re: xDX FPGA IOPT workflow in VX.2
          mike_gibling

          FPGA Part Wizard

          Within the FPGA Part Wizard you can limit the number of Pins on the symbol and also further partition your device, as the wizard is dynamic you can very easily adjust your automated symbol set sizes before exporting them to the library.

          In VX.2.1 (to be release soon) the FPGA Part Wizard has been enhanced to view a selected page border and to read the xDX embedded symbol editor default property definitions and add them to your automated FPGA symbols.

           

          Embedded IOPT Symbol Generator

          Alternatively after using the embedded IOPT symbol generator to create your “customized FPGA partitions” you may publish your FPGA Part/Symbol set to the library

           

          Library

          Once in the library you may edit the symbols as you wish but of course care should be taken to keep the symbols accurate, It may help to duplicate symbol and dual edit the symbols to remove pins

          Rules:

          1.  Library to be at same revision as IOPT project

          2.  Part & Symbol Type = FPGA

          3. Part must have one swap group for all pins without “power gates”

          4. Symbol set to retain the Pin properties

               a.       FPGA Pin Function

               b.       FPGA Pin Name

               c.      FPGA Signal Name

          5. Symbol set to retain the Part properties

               a.      FPGA WIP

               b.      FPGA Device

               c.      Frozen Package

           

          Regards

          Mike Gibling

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          • 2. Re: xDX FPGA IOPT workflow in VX.2
            lanelone

            Thank you for such detailed explanation. Now I am sure I was not trying to do impossible things. So I dediced to test the whole process again. The FPGA I am working on is the Microsemi(Actel) Igloo2 m2gl050.

             

            If I just open and save a symbol created by the FPGA Part Wizard the file changes.

            before save in the xDX Symbol Editor:

            P 2 0 762000 508000 762000 0 2 0

            L 508000 762000 254000 0 2 0 0 0 MSIOD145PB6

            A 0 762000 254000 0 1 0 FPGA Pin Function=MSIOD145PB6

            A 0 762000 254000 0 3 3 #=U1

            A 508000 762000 254000 0 2 3 FPGA Pin Name=MSIOD145PB6

            after save in the xDX Symbol Editor:

            P 2 0 762000 508000 762000 0 2 0

            L 508000 762000 254000 0 2 0 0 0 MSIOD145PB6

            |TVRNT 2 508000 762000 2 8

            |TVRNT 3 508000 762000 2 8

            |TVRNT 6 508000 762000 2 8

            |TVRNT 7 508000 762000 2 8

            A 0 762000 254000 0 1 0 FPGA Pin Function=MSIOD145PB6

            |TVRNT 2 0 762000 2 9

            |TVRNT 3 0 762000 2 9

            |TVRNT 6 0 762000 2 9

            |TVRNT 7 0 762000 2 9

            A 508000 762000 254000 0 2 3 FPGA Pin Name=MSIOD145PB6

            |FNTSTL 0 0

            |TVRNT 2 508000 762000 2 8

            |TVRNT 3 508000 762000 2 8

            |TVRNT 6 508000 762000 2 8

            |TVRNT 7 508000 762000 2 8

            A 0 762000 254000 0 3 3 #=U1

            |TVRNT 2 0 762000 2 7

            |TVRNT 3 0 762000 2 7

            |TVRNT 6 0 762000 2 7

            |TVRNT 7 0 762000 2 7

             

            The xDX IOPT tool does not accept lines beginning with "|TVRNT"  throwing various logic errors about unrecognized statements in symbol files. If I manually remove all such lines from the edited symbol file everything works and I can open the xDX IOPT again. Of course, the symbols need to retain all the properties you mentioned.

            I think the xDX IOPT tool should be updated to ignore these lines automatically.

             

            Regards

            Radek L.

            • 3. Re: xDX FPGA IOPT workflow in VX.2
              mike_gibling

              Radek,

              Please log an SR with customer support and tell them I have reproduced the issue in VX.2.0 - good news it is working fine in VX.2.1 which will be released soon

               

              Mike Gibling

              • 4. Re: xDX FPGA IOPT workflow in VX.2
                lanelone

                OK, I will report this issue. Many thanks for your support. Keep up the good work!

                Radek L.

                • 5. Re: xDX FPGA IOPT workflow in VX.2
                  mike_gibling

                  Radek,

                   

                  Having reproduced the issue, I tried on the second day and like our engineering tests I could not reproduce it again - apparently one possible cause it the status of the central library - in my case apparently it did not update to VX.2.0 correctly

                   

                  Regards

                  Mike Gibling

                  • 6. Re: xDX FPGA IOPT workflow in VX.2
                    mike_gibling

                    Radek,

                     

                    I have now a video to reproduce can you supply me a SR# that you logged and your company name so that I can attach them to my log

                     

                    Many thanks

                    Mike Gibling

                    • 7. Re: xDX FPGA IOPT workflow in VX.2
                      lanelone

                      Hello Mike,

                       

                      I do not have sufficient permissions set on my account. I had to ask our SW admin who has full access to the Support Net. SR# is 2903536187.

                      I hope we did it right.

                       

                      Best regards,

                      Radek L.