5 Replies Latest reply on Apr 25, 2017 11:19 AM by chris_balcom

    Multiple grounds in Calibre LVS


      I am taping out a mixed-signal IC with multiple grounds - DVSS, AVSS, APR_GND etc. These will shorted off chip on the PCB. How can I specify this while setting up LVS to avoid stamping conflicts and other errors? I tried using psub but this does not work.

        • 1. Re: Multiple grounds in Calibre LVS

          How is your rule file set up for psub? If you tried psub and still see stamping conflicts, could it be caused by true problems?

          • 2. Re: Multiple grounds in Calibre LVS

            HI Chris,


            I am using the colon operator to virtual connect these nets on the layout. Can this work on the schematic as well? If I have nets on the schematic as VSS:1, VSS:2 etc, will they all be extracted out as VSS?


            In general, what is the procedure to specify the two disparate grounds will be connected off chip?



            • 3. Re: Multiple grounds in Calibre LVS

              I think it's important to decide how you ideally want to check them within the chip for a robust check. If they are separate within the chip, maybe it will be good to check that they truly remain separate within the chip instead of virtually connecting them?


              On the other hand If there is no consequence for VSS1 to be accidentally shorted to VSS2 in the layout, it is good to confirm that.


              Is the schematic designed differently than the layout? For instance, is there only one ground in the schematic while there are multiple grounds in the layout? If the schematic has separate grounds to match the layout separate grounds then maybe it will be good to check that the grounds in the layout match the grounds in the schematic without virtually connecting them together?


              Is it that you need to virtually join them for simulation purposes or is your main concern to get through LVS smoothly and accurately?

              • 4. Re: Multiple grounds in Calibre LVS

                For simulation purpose, I would actually like them separate and that is how they are in my schematic. I want to get through LVS accurately - that is my main criterion.


                However, the problem is that I have substrate taps on each of these ground domains and this is causing my LVS to fail because it thinks the substrate should be one net (this is what I can understand from the error messages to best of my knowledge). Appreciate any suggestions.

                • 5. Re: Multiple grounds in Calibre LVS

                  The Calibre SVRF rule file usually has some special layer that the rule file developer designed into the layer derivations so that the substrate could be artificially separated from one region to another. For instance, if the chip was mostly connected to VSS1 and then in one area the circuitry was connected to VSS2 then a certain marker layer could be drawn around the VSS2 related block and then the substrate inside that marker layer would be separated from the rest of the design by a tiny cut line along the edge of the marker layer. With this, the substrate is formed in different regions instead of one large continuous region.