I don't have an answer, sorry, just another question:
In my understanding, ICT data is an ASCII list of probe locations (netname and X-Y coordinate)
I could see trying to map those locations onto a PCB layout (to fix or lock test point vias, for example)
but how could you possibly map probe locations into a SCHEMATIC?
David maybe talking about a different ICT, i.e. which I think stands for Interconnectivity Table. Like you, I am used to ICT standing for In Circuit Test
That makes perfect sense...