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Edge castellations

Question asked by d_circuitt on Sep 8, 2017
Latest reply on Sep 12, 2017 by vinayarora

I'm using PADs layout to create an edge castellation, the process being used at the moment is to place a via on the board edge and then have the via cut in half to give a plated arc. The problem I'm encountering is the design verification is of course giving board outline violation errors. The question is there a way to either create a proper edge castellation that wont cause this error or is the only way to ignore the error?

 

Any help on this will be appreciated! 

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