When a placement or route operation fails the tools only say "can't resolve immovable metal conflict" or soemthing like that with no detail as to where/what/layer/conflict this actually is. Clearly it "knows" this internally but it would save countless hours of experimentation if full detail was reported by the tool.
This has been implemented with the 2007 release for routing already. The "Plow failed" message of the past is now much more meaningful.
For the place mode there are no current plans to implement in place mode since we already highlight graphics for violations.
Plane Obstructs on All Layers: Support of an "all layers" option for a Plane Obstruct object is a long existing request on Supportnet.
There could be an "All Layers" and an "All but.." option.
What are your ideas on this?
Does anyone have resolved this with Automation already?
The Cell Editor's BGA pin naming could be improved using a matrix to assign all the pin numbers in one shot (i.e. A1 ... A20, B1 ... B20, etc. ...) and also skipping the unusable suffixes (e.g. I, O, Q, etc. ...)
This is not planned in engineering right now.
This is a great application for using Automation. Who has done this already with the Automation language?
This could be a great project for the community... and can be resolved independent from engineering.
There should be a possibility to add a few user-widths in the change width popup on manual routing. The minimum, typical and expansion are to less values.
One user has created an Automation script and shared it on the voting page. Here is the posting:
"I've been busy this weekend and have made some changes to my TWC app. I have uploaded V7 to www.paradigm-solutions.co.uk/twc.htm. Let me know if you find any issues."
Keep discussing here about this use case and other Ease of Use ideas.
We works with Power Electronics and requests more functionality in this area. In particular to be able to define a current for a trace segment . It should be possible to define the current in schematic on a pin-to-pin level. In the PCB, using the copper thickness and PCB material, it should then be possible for VBPCB to calculate the correct trace width. The system should also be able to cope with split traces when the traces run parellel on the same or on separate layers. This calculation must also work for partial power planes (min. connection area) In DRC/Hazards, the system should be able to report when 2 current carrying traces are placed over another, or cross each other. In these positions the current carrying traces would cause local warming and softening of the PCB material. The system should also report min. trace width violations using the current, thickness, material calculations. In setup, it should be possible to define calculation factors that are dependant on PCB material, layer and max. temperature.
Is this really required in Expedition?
Should this be part of the Power Integrity Analysis solution?
What role would CES play?
Keep discussing and completing use cases for this
Rather than dedicate lots of effort to what I would consider fairly minimal use case improvements spend some quality time actually listening to thouse who spend many thousands of hours using the tool getting their feedback on the poor ergonomics of the basic operations already supported by the tool. What is currently OK could be made "great" for not much work and would save EVERY user many hours of frustration and wasted mouse clicks speeding up the design process and saving us all money.
This is a good discussion and should lead to usability improvements with the next major release.
Watch the comments on the Ideas page and keep going... gathering more use cases and ideas around the usability aspects here and vote!
The ability to add star points which connect multipule nets together at a single point, or at any layer on a single ( or multipule) via. This must not result in a million DRC error. It must also be processed by Hyperlinx, ICX and the new power tools. I have been requesting this for at least 15 years both in Boardstation and DX. Other EDA suppliers can do it, why not MENTOR. !!!!@@@!!!!
This currently not planned.
If this is a priority you should discuss and vote!
Provide a same net SMD pad to via clearance setting in Netclasses and Clearances. Currently in Expedition, Pad via clearances are not ignored for pads and vias on the same net. This impacts both placement and routing, because components need to be placed further apart than is necessary, and must have longer (higher inductance) connections in you maintain the clearances needed for other pad-via rules. When the clearances are adjusted to account for the same net fanout, it allows violations to occur in other portions of the design.
We will need more use cases and specific understand where and how this applies.
Please discuss details how this is important to you!
When switching between Place, Route & Draw Modes, the toolbars do not retain their positions and must be moved around. When I place the toolbars for each mode, I want them to stay there when I return to that mode. Reference DR#140151
Also in Xtreme PCB the toolbars are "travelling around".
If i call a software Expedition Enterprise, I have to add configuartion options for emterprise usecases.
Each user keeps his settings, on whatever project he is working.
This issue has not been reported as issue before. Please discuss and explain further and vote
When we define a Rule Area around a component and route into or out of said component, the trace gets a vertice added where it crosses the rule area. If the vertice occurs on a 45, it is very diffcult to drag the 45 because the vertice wants to remain pinned at the crossing point. It is VERY difficult and time consuming to manually "gloss" traces in this transition area. I'd like to see the vertice removed or changed to another type of vertice that does not affect the interactive trace routing.
This is something we are looking at. Please discuss further and provide additional input.
During interactive routing show the trace being drawn, as well as the needed clearance insulation. This insulation outline, is what makes drawing so much more clear. In Expedition / XE it is not visible when the trace that you are routing will collide with a previoulyÂ designed trace.
Has anyone seen how this is being done in PADS?
Would this be an appropriate solution?
Lets expand the use cases to understand the different applications where and how this is useful.
The Pen width is not correctly displayed. The characters appear the same regardless of the pen width. You can only see the actual text in the Gerber file of a PDF file.
With EE2007.5 we will be providing vector fonts.
Please review this idea after evaluating the solution in the upcoming release and discuss.
Today it is too difficult to drive the dialogs using Automation. You must first bring up the dialog box and then choose the checkbox or other button etc. You have to know the name of dialog box and the name of button etc. It would be easier if we can automatically record and save the sequence of what we do with dialogs into a macro and later we can use this macro in Automation. This method is like automatically macro recording in EXCEL.
This is not planned and out of scope.
What are use cases?
Why is this important?
What does it do that Automation cannot do?
What does it add to the pretty automated Expedition?
the issue here is the Batch DRC and also CES.
If we add additional trace widths in the layout usinge the automation tool (I have tested), we get hundereds of messages due to wrong trace widths.
In 2007.5 we can easily mark them as OK, but thats not the right approach. There should be an easier way to switch by RMB/keyin to a new width you want to proceed to route with (min < New width < Max).
At the end, neither CES nor Batch DRC shoild complayin here anyway, because the new with is inside the allowed rules.
Also for differential pairs there is a need to have such a feature and a smooth transition incuding the diff pair spacing shoule be available.