You might have noticed also that you can also get the properties, including delay, of an individual segment, but not a group of trace segments. HyperLynx SI is not intended to verify layout guidelines like this. It is designed to run simulations of nets as they are designed. For SI, the simulation is more important than layout guidelines, so you might go ahead and run simulations.
Mentor has another tool that is intended for verification of design guidelines and finding more geometric patterns like this. HyperLynx DRC has many useful built-in rules for checking such things, and you can create new rules to check almost anything geometry or layout related. You can get a free version of HyperLynx DRC that includes the ability to check differential skew of routed nets. Look here HyperLynx Design Rule Checking Starter Editions - Mentor Graphics for the details.
I hope this helps you in the verification of your design layout.
Many thanks for this and the link to the DRC tool - I will take a look shortly.
The reason I was interested in HyperLynx SI for this task is that I need to skew based on time delay rather than length. This means that I need to be able to simulate the net delay based on stackup, via design, bonding wire length etc. Does the DRC tool allow you to do this or is it a purely a tool for defining length constraints? If not do you know what the best way to do this would be?
It sounds like what you really want is to simulate the diff nets in HyperLynx SI and examine the waveforms at the receiver die. The most accurate results come from using models for the specific components in your design, but you could also use generic models of the same technology in order to judge the correct routing of the PCB.