2 Replies Latest reply on May 22, 2018 11:15 AM by weston_beal

    FPGAs Package Capacitor Consideration during PI Analysis



      I am trying to use Hyperlynx PI (ver. 9.2) to do decoupling analysis for Xilinx-Kintex7 fpgas. The user guides of these FPGAs explicitly mention that these FPGAs have enough on-package decoupling capacitors that we don't need to add any further ceramic capacitors on PCB to bring down the impedance for mid - high frequencies. Kintex-7 even provides the values of these on-package decaps (C, ESL, and ESR).

      How can I feed these inputs into Hyperlynx PI while doing decoupling analysis. I want to model these along with xilinx's recommended bulk capacitor and VRM model to check the impedance profile. In addition, how can we input the package inductance of these FPGAs?



        • 1. Re: FPGAs Package Capacitor Consideration during PI Analysis

          Hi Chandan - thanks for your post. I am going to move it to the Hyperlynx community where it will receive greater visibility by other Hyperlynx users. Where you have posted it is for general community questions and suggestions.

          • 2. Re: FPGAs Package Capacitor Consideration during PI Analysis



            HyperLynx PI is really optimized for analysis of the PCB. What you want to do is more of a general purpose simulator task. From the point of view of HyperLynx PI, you probably want to focus on the low-frequency decoupling of the PCB. Does Xilinx provide any power noise or impedance recommendations for frequency bands of interest?


            If you want to see the impedance including the package and die, you need to run a few extra steps. Create a LineSim schematic of the package, on-package capacitance, and die. Extract S parameters of this network at the pins.

            Export the power plane pair (for example VDD and VSS) for analysis into LineSim. Assign the extracted S parameters of the component to the appropriate component pins and run the decoupling analysis in LineSim.