Is this a pre or post layout simulation?
I've only done post layout sim and then work backwards to address timing, margin or S.I. issues like overshoot etc..
I always had my design rules, Stackup's and impedance's defined and then simulated at the end end of my layout.
I guess you could add all of your driver/receiver pairs individually and simulate the whole data bus for a number of clocks or stimuli but that seems but that seems way too involved at least for me.
For me working it backwards was easier because the DDRX wizard ran the whole simulation from the board and then reported to me all of the required data plus my pass fail .. if something was amiss I could always push from the layout back to linesim and make theoretical adjustments to correct and then correct my layout and re-run.
This at least would allow you to run both read and write analysis on your entire chain using your ODT's etc.
There was a a great webinar on running sweeps of the terminations it may still be out there then maybe it will give you an idea for setting up other batch functions.
Unfortunately no, I think I mis-spoke, It was a webinar on running sweeps in the DDR simulation.
It was a bout a year ago.. I'd have to dig through my emails and see if I had the link to the webinar.. maybe it was recorded?