2 Replies Latest reply on Jun 11, 2018 12:56 AM by davide.palmisano@nokia.com

    duplicated holes in BD to EE translation



      I translated a BA/BS design to xDX/Xlayout under VX2.2 successfully. I got double holes for some vias used in QFN thermal pads

      Did anybody get the same problem?

      how did you solve it?

      Thanks in advance


      Best regards