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duplicated holes in BD to EE translation

Question asked by davide_palmisano on Jun 7, 2018
Latest reply on Jun 11, 2018 by davide_palmisano


I translated a BA/BS design to xDX/Xlayout under VX2.2 successfully. I got double holes for some vias used in QFN thermal pads

Did anybody get the same problem?

how did you solve it?

Thanks in advance


Best regards