Those two netlists look identical... they both seem to be from a layout and the pin name difference isn't showing there. What pin names are described in the error message?
I'm so sorry. I put wrong schematic netlist, there is correct netlist:
.SUBCKT rhigh a b
*.PININFO a:B b:B
RR2 a b sub! 1.745K $[rhigh] m=1 l=6u w=4.6u b=0 ps=180n trise=0.0
RR1 a b sub! 1.745K $[rhigh] m=1 l=2.51u w=2u b=0 ps=180n trise=0.0
RR0 a b sub! 1.745K $[rhigh] m=1 l=960n w=845n b=0 ps=180n trise=0.0
I have error notification only in lvs.report file: Error: Components with non-identical signal pins
That style of 3rd pin netlist format isn't supported... Are you able to get to this TechNote link in SupportCenter?
The Calibre Verification User's Manual has related details for the substrate pin usage in the section "Resistor Element" in the "Spice Format" chapter.
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Thx. a lot.
For other people why faced with the same problem, in auCdl section delete sub terminal from termOrder section and add "SUB" in the instParameters section.