medan

Question abot LVS: "Error:    Components with non-identical signal pins."

Discussion created by medan on Jun 8, 2018
Latest reply on Jun 12, 2018 by medan

I have resistor device with 2 terminal + 1 inherit (sub!)

DEVICE R (rhigh) Rhigh_edge GP_connect(POS) GP_connect(NEG) bulk(SUB) <edgeLayer_Rhigh>

 

In the test I put 3 resistors in parallel.

 

In layout netlist I have following:

>> .SUBCKT rhigh sub! a b

  ** N=3 EP=3 IP=0 FDC=3

  R0 a b 1739.66 L=9.6e-07 W=8.45e-07 $SUB=sub! $[rhigh] $X=2650 $Y=10100 $D=36

  R1 a b 1744.8 L=2.51e-06 W=2e-06 $SUB=sub! $[rhigh] $X=7745 $Y=9460 $D=36

  R2 a b 1745.31 L=6e-06 W=4.6e-06 $SUB=sub! $[rhigh] $X=16530 $Y=8040 $D=36

  .ENDS

 

In schematic:

>> .SUBCKT rhigh sub! a b

  ** N=3 EP=3 IP=0 FDC=3

  R0 a b 1739.66 L=9.6e-07 W=8.45e-07 $SUB=sub! $[rhigh] $X=2650 $Y=10100 $D=36

  R1 a b 1744.8 L=2.51e-06 W=2e-06 $SUB=sub! $[rhigh] $X=7745 $Y=9460 $D=36

  R2 a b 1745.31 L=6e-06 W=4.6e-06 $SUB=sub! $[rhigh] $X=16530 $Y=8040 $D=36

  .ENDS

 

LVS report following error:  "Error:    Components with non-identical signal pins."

Could you pls. tell me how to match "sub!"?

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