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How to connect a hierarchical port to a global net?

Question asked by kjsewell on May 28, 2019
Latest reply on May 31, 2019 by robert_davies

Hello everyone,


I am using PADS (DX) Designer VX.2.5 (standard) Update 2 in netlist flow. Pictures are shown below of the schematic and issue in question:


Image 1: toplevel hierarchical block. The port named "CTL_SW_CM" is connected to J3.


Image 2: Inside the top-level hierarchical block. The "CTL_SW_CM" hierarchical port is connected to the "Control_Position_Indication" block.

Image 3: Inside the "Control_Position_Indication" block. The "CTL_SW_CM" hierarchical port is connected to the global net "VUR". My goal is to connect the "CTL_SW_CM" hierarchical port to the "VUR" global net. However, several warning messages are generated when I run the "PCB Interface" dialog and the port is not connected to the global net as I had expected. Instead the schematic connection between "CTL_SW_CM" and "VUR" is ignored.

Image 4: The documentation for Warning 5727. Unfortunately, I need an example of how to do this. I believe going from hierarchical port to global net may be a special case which is why my attempts to follow the solution have failed.



As stated in the caption for image 3 I wish to connect a hierarchical port to a global net. The documentation states that for Warning 5727 the solution is that I should "Use a bus ripper to alias a global net to another named net." Unfortunately I do not know exactly how to carry out this procedure.


We known that we can connect the nets with a zero ohm resistor but in this case that won't work for our design. The two nets need to be connected directly by copper (without a physical resistor) on the PCB.


I have tried several solutions from the knowledgebase documentation but each attempt by me has has failed. Based off of my experience I am going to assume that I am interpreting the directions for the solution incorrectly.


That bring me to my question: can somebody show with screenshots or a video how to tie a hierarchical port to a global net in PADS (DX) Designer Standard netlist flow? (and not have the PCB Interface tool generate the warnings shown in image 4)



The Engineering Team at Western Reserve Controls, Inc.