I'd like to contribute a few ideas to the discussion you started. I'd be very interested in other ideas from more people too.
From my perspective "seeds" are an important part of "devices", and "promotion" is another way of saying "moved to a higher level". So with those two ideas together, "seed promotion" can be thought of as another way to describe a case where devices ended up at higher levels than expected.
A device in Calibre LVS is comprised of the seed shape (device body) and pins. For a mosfet the seed shape is typically the intersection of poly and diffusion. The pins are typically the source and drain (typically defined as diffusion NOT poly) and the gate pin (typically poly), and a bulk pin (typically a well, or substrate).
One of the most common causes of seed promotion is the calculation of certain properties that relate to the device, but aren't the same for every placement of that device. These properties might be relative to the seed shape or the pins associated with the seed shape. AS and AD are examples of properties that have caused problems of this nature for years. If a source pin on a device, in a cell, has a certain AS property value that is different in one placement than another, then that device can't really be described accurately in both locations by using just one property value.
W and L have never been a problem because the W and L of a device in a cell is typically the same in every placement of that cell.
AS and AD are not always the same because the calculations of these values can change depending upon the relationship of cell placements with each other. for instance, a cell could be placed once, with no cells nearby, and the AS/AD would be calculated with a certain value. Then the same cell might be placed somewhere else as a pair of mirrored cells where the source pins of the mosfets are shared. The AS/AD properties would be different in this case. The subckt representing the placed cell would no longer be able to reflect accurate values for AS and AD because the values would be different for different placements. the affected transistors would typically be "promoted" up until the devices were present in some higher subckt (flattened in other words) so that each could now be represented with different AS/AD values reflecting the different placements of the same cell.
There is much more that we could discuss in the area of seed promotion but before I go further it might be good to stop and check to see if this is the type of information you were interested in.
Thanks alot for the nice explanation. It was very much helpful to understand the Seed Promotion.
Actually my LVS run says its correct, but when I run XRC, my LVS is failed. I dont know what to do now. My designers wanted the spice netlist which should be LVS clean during the XRC run.
You might try adding LVS PUSH DEVICES SEPARATE PROPERTIES myfile.pdsp to your rulefile. It's helpful during connectivity extraction and LVS comparison and xRC. Here's a TechNote that discusses it in a little more detail.
Just to add that "LVS PUSH DEVICE" and "SEED PROMOTION" are 2 commands which could have a important impact on the run time. You surely need to be aware of it, if you work with big design. Indeed these 2 commands reduce the scalability(like a flattening).
Another related question: We have seen that calibre lvs has a long runtime if it hits seed promotions.
LVS PUSH DEVICES YES
LVS PUSH DEVICES SEPARATE PROPERTIES filename
ma ke the runtime faster?
Maybe but you should better look in the transcript which operations need a lot of time and just use PUSH on the layer or derived layer used by this long operation.
Have a nice WE.
I will not be able to do that though, part of the rule deck is encrypted and the seed promotions are being caused by the encrypted layers.