I have a question about gate level simulation with back annotation using Questa.
As described in Questa manuals, I have a situation that I cannot start simulation because of errors by the SDF annotator while loading the design.
Also as described in Questa manuals I used "+nosdferror option with vsim to change SDF errors to
warnings so that the simulation can continue."
Using this solution am I just "masking" my current problem with SDF annotator ?
Does my simulation with +nosdferror option really represent a real gate level simulation with SDF back annotation ?