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Hyperlynx : DDR3L Batch Simulation Data Read Fail

Question asked by o_asulin_q9mcc on Sep 3, 2020
Latest reply on Sep 7, 2020 by o_asulin_q9mcc

Hi,

After having some fails issue performing post layout batch simulation for READ, i have tried to perform Linesim simulation to verify my topology.

 

Our board use one controller and two DDR devices (As if they were two DIMMs). The DATA/DQS topology is daisy (i..e routing data from controller to the first device and then to the second device) 

My LineSim design has the above devices with their IBIS model and are connected with single trans line (i.e. no VIA, etc. for the simulation). The LineSim include single data line and it's associated DQS line.

I have swept the ODT values for the DRAMs and the controller.

I have also created Timing model for the controller per the datasheet.

in the DDR wizard, i set the topology as 2 slots with single Rank.

 

I always fail (Typ corner) while reading from the far device. Reading from the closer device is successful (typ).

 

p.s., placement constraints brought me to the daisy chain topology rather than a balance-T topology (for the data).

 

The fails are both in setup and in hold.

Can you help understand what could be the issue in such an "IDEAL"  (no routing/via effects etc) simulation? only the "FAR" device fails.

 

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