4 Replies Latest reply on Jun 24, 2010 5:20 PM by yijun_tong

    empty cells ??? help plz :)



      i wonder about a problem opening a layout in calibre DESIGNrev

      when i open the layout , in the terminal it reports this message (for all cells in the layout).. an example of this message is as following :

      WARNING: Cell CLKINVX1 is referenced but not defined. Empty cell used.

      N.B. this is an ASIC design . and i use synopsys design compiler for synthesis and cadence first encounter for placement and rounting . calibre for verification .


      can u plz explain for me this message ?


      is this warning will affect my DRC , LVS and PEX run ?


      thx very much 

        • 1. Re: empty cells ??? help plz :)

          That sounds like the lower level cells don't exist in the layout database. It sounds like CLKINVX1 isn't in the layout. (as opposed to CLKINVX1 being there, but being empty). And then the end result is that an empty cell is used in it's place.


          To confirm this, you might try to run DRC on that same layout file, while using CLKINVX1 as the LAYOUT PRIMARY.

          This experimental DRC run should prove whether it exists or not. If it exists then the job should run. If it is missing then the job should abort.


          Is CLKINVX1 really supposed to be used in the layout? Is it possible that there is just a reference to CLKINVX1 but that the full contents of CLKINVX1 aren't really supposed to be there?


          One last possiblity is this... are you using version 2008.1 ? There was a bug that related to a certain way of deleting cells using custom TCL script, and it may result in nuisance messages like this.

          • 2. Re: empty cells ??? help plz :)

            "thank you very much chris for your answer

            i have run DRC , as you mentioned , it runs correctly .

            i added tsmc090 as library folder in the design.stream_in" file 

            'libName  "tsmc090"

            and also , i added the .tf tech file as following in the same stream_in file :

            'techfileName  "./tsmc090_9lm_2thick.tf"

            now the error is not "can not read layout . abort " , it is as following :

            Creating Design Database ...
            Converting Design ...
            Warning: no module declaration for module ADDHXL first encountered in module IFFT_PTS_1_DW01_inc_6_0_0

            ....same warning for all cells .

            then " can read source , abort "

            important note : the source is in verilog format !


            additional question : must i add any technology files ? .lef files ? .db files ? if i must do it , how can i perform adding them ?



            thx for helping me

            • 3. Re: empty cells ??? help plz :)

              I'm not familiar with those messages, hopefully someone else may recognize them and be able to help.

              • 4. Re: empty cells ??? help plz :)

                DESIGNrev produces warning when seeing cells referenced but not existing.


                You can fix this by loading the file into DESIGNrev and save it out using the "Write all cells and references" option.  DESIGNrev will automatically create the empty cell when reading it in and with the option it would write those cells out.