atamez

xRC gate-level extraction - calibre view generation, but symbols have pins that are buses (4-bits wide)

Discussion created by atamez on Sep 6, 2010
Latest reply on Nov 9, 2010 by atamez

I have top-level cell with approximately 1000 instances of MY_CELL.  MY_CELL has about 10 pins, but a couple of these are 4-bits wide (i.e. IN<3:0>).  I think I am using the hcells/xcells correctly but when the calibreview is generated it is not able to match the instances of MY_CELL with the symbols in the library.  I've tried a few different syntaxes in the calview.cellmap entry for MY_CELL but no luck.  Any suggestions for getting this to work?  I can provide a sample netlist or log files if it will help.  Thanks!!

Outcomes