Suppose following use case:
a central libary is created for EE full flow , and add key properties in symbols to support back-end Allegro. Another Allegro symbols(cells) library is maitaned seperately. the schematics is created using the central libary, and use icdb. so user can get full advantages if both logic designer and layout designer using same EE tools. However some of layout designer only use Allegro, so the Allegro layout designer export .tel netlist and import theio netlist to Allegro. If don't take care of constrants tranfering and re-use blocks, the most risk I guess is the back-annotation of pin swappings, gate swappins to schematics from Allegro.
Are there other risks? Suppose there is no other risks(for example, Mentor stop to support keyin flow Dxdesigner-Allegro in near future), I will begin to solve the back-annotation issue.