wangyl

Spare cell that all input tie to VDD and output float, miss match in 40nm LVS

Discussion created by wangyl on Jul 22, 2011

Hi :

    I meet a issues in 40nm lvs design.

    My design is a 40nm digital design, in the design we have lot of spare cell have two input tie to VDD and only one output is float.

    The LVS report is not clean, the instance number is all matched. it is report like below.

 

     LAYOUT                                                SOURCE

 

     CELLA                                                ***No similar instance***

     A:net1                                                 ***No similar net***

     O:3                                                     ***NO simiar net****

 

   ***No similar instance***                          CELLA

   ***No similar net***                                 A:net2

   ***NO simiar net****                               O:unconnected

 

Did we have soltion for this issues?

    Many thanks

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