1 Reply Latest reply on Sep 1, 2011 9:53 AM by weston_beal

    HyperLynx Batch Mode Report;

    uanozie10

      I have a delay question about the report below:

       

      NET = M0_A0
          Nets coupled during crosstalk simulation
            =none
          Nets coupled during high-accuracy simulation
            =none
         SIGNAL-INTEGRITY SIMULATION RESULTS -------------------------------
         Driver     Receiver   Rnd Rise Delay(ns) Fall Delay(ns) Overshoot(V) Crosstalk(V)     ERROR FLAGS
         Device.Pin Device.Pin Rbn   Min    Max     Min    Max    rise   fall  rise   fall    rise     fall
         U16.G7       U1.H8     1   0.424  0.964   0.426  0.967  0.070  0.118   NA     NA   -------  -------
         U16.G7      U35.H8     1   0.313  1.040   0.322  1.027  0.090  0.145   NA     NA   -----N-  ---M-N-
         U16.G7      U34.H8     1   0.175  1.174   0.181  1.171  0.103  0.134   NA     NA   -----N-  ---M-N-
         U16.G7       U3.H8     1   0.313  1.044   0.320  1.039  0.076  0.128   NA     NA   -----N-  -----N-
         U16.G7       U5.H8     1   0.619  0.822   0.627  0.819  0.131  0.184   NA     NA   -------  -------
         U16.G7      U37.H8     1   0.638  0.820   0.653  0.821  0.136  0.192   NA     NA   -------  -------
         U16.G7      U36.H8     1   0.539  0.895   0.550  0.881  0.139  0.198   NA     NA   -------  -------
         U16.G7       U4.H8     1   0.543  0.887   0.550  0.876  0.126  0.182   NA     NA   -------  -------
         U16.G7       U2.H8     1   0.194  1.163   0.192  1.167  0.089  0.124   NA     NA   -----N-  -----N-
          max. rising overshoot allowed  = 300 mV
          max. falling overshoot allowed = 300 mV
          min. delay allowed             = -5.000 ns
          max. delay allowed             = 1000.000 ns
          max. peak crosstalk allowed(+-)= 150 mV
          SI high-accuracy threshold(+-) = 200 mV
           ** Warning(Severe) ** Signal-Integrity Limits Exceeded!

          Longest Simulation Time: 5.476ns
         INTERCONNECT STATISTICS -------------------------------------------
           total metal delay ............ 744.865 ps
           minimum metal Z0 ............. 48.1 ohms
           maximum metal Z0 ............. 53.1 ohms
           total metal capacitance ...... 14.7 pF
                (M0_A0 .................................... 14.7 pF)
           total metal inductance ....... 37.8 nH
                (M0_A0 .................................... 37.8 nH)
           total metal resistance ....... 905.2 milliohms
                (M0_A0 .................................... 905.2 milliohms)
           total metal length ........... 004.447 in
           average metal Z0 ............. 50.7 ohms
       

      Is the total signal delay from driver---->metal (PCB) interconnect----->Receiver =

      Rise Delay Max + total metal delay ?

      Example U16.G7 ---->metal (PCB) interconnect-------->U5.H8 = 0.822ps  + 744.865ps = 1566.865ps

      Is the Rise Delay measured at the receiver input or at the driver output?

       

      Thanks

        • 1. Re: HyperLynx Batch Mode Report;
          weston_beal

          The Min/Max Rise/Fall Delay numbers are measured from actual simulations. The metal delay is calculated from a simple formula that includes only the traces without any effects of the ICs connected to them. These are completely independent measurements. The simulation results take longer to create, because the tool actually simulates the nets. The metal delay results are a fast approximation, but not good for timing constraint verification.

           

          You should also review the BoardSim User Guide regarding compensated flight time. The simulated delays actually measure the time from a reference load waveform to the receiver waveform logic thresholds. It is important to understand this measurement if you use the simulated delays for actual timing calculations in your system.